SHAKTI is an open-source initiative of the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras. SHAKTI's goal is to produce production processors, System on Chips (SoC), development boards and a software platform based on SHAKTI.

Class E

An Embedded class processor, built around a core in three stages, in order. It is intended for low-power computing applications. It is capable of running basic RTOS, such as FreeRTOS, Zephyr and eChronos.

Applicability: smart cards, IoT devices, engine controls and robotic platforms.

Class C

A class of controller processor, which targets the workloads of mid-level applications The kernel is highly optimized, in 5 steps, in order, with MMU support and the ability to run Linux and Sel4 operating systems.

Applicability: calculates / controls applications in the range of 0.5-1.5 Ghz.

Class I

Equipped with performance-oriented features such as out-of-command execution, multi-threading, aggressive branch prediction, non-blocking caches and deep pipeline stages.

Applicability: computing, mobile, storage and network segments. The target operating range is 1.5-2.5 Ghz.

Class M (Multicore)

A mobile class processor with a maximum of 8 cores, the cores being a combination of class C and I cores. Tile-Link is used as a coherent cache interconnection used together with transaction / bridge adapters to AXI4 / AHB to connect quickly and / or on slow peripherals. The TileLink topology is customizable to allow optimizations for different power / performance targets. In typical configurations, a base complex of 2 or 4 cores is expected to share an L2 cache. L3 caches are optional and are usually expected to be used in desktop applications.

S-Class (Multicore)

Designed for Workstation and Enterprise servers. The core is an improved version of Class I, with quad-core and multi-threading support. An interconnection of your choice is a coherent mesh fabric based on cache-link. Kernels are expected to use dedicated L2 caches and segmented L3 caches. A maximum number of 32 cores will be accepted. External interconnection is expected to be Gen-Z and we plan to accept multi-socket cache consistency based on a MOESIF-style protocol running on top of the Gen- Z.

Class H (Multicore)

An SoC configuration that targets highly parallel work, HPC and analytical tasks. The cores can be a combination of class C or I, single-wire performance that drives the choice of core. Optional L4 caches and an optimized memory hierarchy for high memory bandwidth. The propulsion of the architecture is on accelerators, VPU and AI / ML and a mesh fabric optimized for up to 128 cores with multiple accelerators per core. Tight integration with a Gen-Z external material is an essential part of the design, as well as storage class memory support.

Class T (Experimental)

A variant of class C that explores tag-based ISAs for object-level security. Designed to support fine and coarse labels. Coarse labels will be used to make a micro virtual machine, such as functionality to mitigate software attacks, such as overcoming the buffer.

Class F (Experimental)

Error-tolerant version of the base class processor. Features include redundant computing blocks (such as DMR and TMR), temporary redundancy modules for permanent fault detection, basic blocking configurations, fault location circuits, ECC for critical memory blocks, and redundant bus fabrics.


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